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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
,VVXHꢀꢁ  
AAL1 SAR Processor  
6.3.2 TUTOPIA as the PHY Layer Device in Single PHY (SPHY) Mode  
The TUTOPIA block functions as a receive UTOPIA block when in SPHY mode. The receive  
SPHY UTOPIA timing signals are compatible with the ATM Forum UTOPIA Level 1 cell-level  
hand-shaking specification (refer to Appendix B, “References”, on page 203). Table 18 indicates  
the AAL1gator II receive SPHY UTOPIA signal names and their corresponding UTOPIA desig-  
nations. The AAL1gator II will not assert RPHY_CLAV unless it has a complete cell to send.  
RPHY_DATA and RPHY_SOC are tristate, except for the cycles following ones in which  
/RPHY_EN is active. RPHY_CLAV goes inactive one cycle after the last data byte has been out-  
put. Figure 64 shows the data output timing for the TUTOPIA block in SPHY mode. The timing  
parameters used in Figure 64 are defined in the table following the figure. All output timing  
delays assume a loading of 50 pF. Refer to section 3.4 “Transmit UTOPIA Interface Block  
(TUTOPIA)” on page 41 for additional information.  
Table 18. Receive Signal Names and Corresponding UTOPIA Designations  
Signal Name  
UTOPIA Name  
/RPHY_ADDR  
RPHY_DATA  
RPHY_SOC  
RPHY_CLAV  
/RPHY_EN  
RxAddr  
RxData  
RxSOC  
RxClav  
RxEnb*  
RxClk  
RPHY_CLK  
Thd  
Tsu  
Tdc  
RPHY_CLK(i)  
Tq  
RPHY_CLAV(o)  
RPHY_SOC(o)  
Tq  
Tq  
D1  
RPHY_DATA(o)  
/RPHY_EN(i)  
D2  
D3  
Figure 64. TUTOPIA SPHY Timing  
ꢈꢇ  
 
 
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