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PM73121-RI 参数 Datasheet PDF下载

PM73121-RI图片预览
型号: PM73121-RI
PDF下载: 下载PDF文件 查看货源
内容描述: AAL1分段重组处理器 [AAL1 Segmentation And Reassembly Processor]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 223 页 / 2148 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM73121AAL1gator II  
Data Sheet  
PMC-Sierra, Inc.  
PMC-980620  
,VVXHꢀꢁ  
AAL1 SAR Processor  
Thd  
Tdc  
Tsu  
TPHY_CLK(i)  
Tq  
TPHY_CLAV(o)  
TPHY_DATA(i)  
TPHY_SOC(i)  
TPHY_EN(i)  
D1  
D2  
D3  
D4  
Figure 67. RUTOPIA SPHY Timing  
Symbol  
Parameter  
Signal  
Min  
Max  
Unit  
TPHY_CLK frequency  
TPHY_CLK duty cycle  
TPHY_CLK hold time  
33  
55  
MHz  
%
Tdc  
Thd  
45  
1
TPHY_DATA,  
ns  
TPHY_SOC, /TPHY_EN  
Tq  
TPHY_CLK-to-output  
delay  
TPHY_CLAV  
12  
ns  
ns  
Tsu  
TPHY_CLK setup time  
TPHY_DATA, TPHY_SOC, /TPHY_EN  
5
6.4.3 RUTOPIA as the PHY Layer Device in Multi-PHY (MPHY) Mode  
The RUTOPIA block functions as a transmit UTOPIA block when in MPHY mode. The transmit  
MPHY UTOPIA timing signals are compatible with the UTOPIA Level 2 MPHY specification  
(refer to Appendix B, “References”, on page 203). Table 20 on page 101 indicates the transmit  
UTOPIA signal names and their corresponding UTOPIA designations. The AAL1gator II will not  
drive TPHY_CLAV unless /TPHY_ADDR was low the previous cycle. The value driven will be  
dependent on whether or not it has room for a complete cell. TPHY_DATA and TPHY_SOC are  
captured when /TPHY_EN is active and the AAL1gator II was selected. The AAL1gator II is  
selected only if /TPHY_ADDR is low and /TPHY_EN is high during one clock cyle, and /TPHY_  
EN is asserted low in the following clock cycle. TPHY_SOC indicates the start of a new cell. If  
the current cell will fill the internal FIFO, then TPHY_CLAV will be deactivated the same cycle  
it is receiving the 49th byte of data if /TPHY_ADDR is low on the previous cycle. Figure 68  
ꢀꢉꢁ  
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