PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Symbol
Parameter
Signal
Min
Max
Unit
RPHY_CLK frequency
RPHY_CLK duty cycle
RPHY_CLK hold time
33
55
MHz
%
Tdc
Thd
Tq
45
1
/RPHY_EN
ns
RPHY_CLK-to-output delay
RPHY_CLK setup time
RPHY_CLK-to-output delay
RPHY_CLAV, RPHY_SOC
/RPHY_EN
2
12
13
ns
Tsu
Tq
5
ns
RPHY_DATA
2
ns
6.3.3 TUTOPIA as the PHY Layer Device in Multi-PHY (MPHY) Mode
The TUTOPIA block functions as a receive UTOPIA block when in MPHY mode. The receive
MPHY UTOPIA timing signals are compatible with the ATM Forum UTOPIA Level 2 MPHY
specification. Table 18 on page 98 indicates the AAL1gator II receive MPHY UTOPIA signal
names and their corresponding UTOPIA designations. The AAL1gator II will not drive RPHY_
CLAV unless /RPHY_ADDR was low the previous cycle. The value driven is dependent on
whether or not the AAL1gator II has a complete cell to send. RPHY_DATA and RPHY_SOC are
tristate, except for the cycles following ones in which /RPHY_EN is active and the AAL1gator II
was selected. The AAL1gator II is selected only if on the falling edge of /RPHY_EN, /RPHY_
ADDR is low. RPHY_SOC indicates the start of a new cell. RPHY_CLAV goes inactive one
cycle after the last data byte has been output if /RPHY_ADDR is low at the time. Figure 65 shows
the data output timing for the TUTOPIA block in MPHY mode. The timing parameters used in
Figure 65 are defined in the table following the figure. All output timing delays assume a capaci-
tive loading of 50 pF. Refer to section 3.4 “Transmit UTOPIA Interface Block (TUTOPIA)” on
page 41 for additional information.
Thd
Tdc
Tsu
RPHY_CLK(i)
/RPHY_ADDR(i)
Tq
RPHY_CLAV(o)
RPHY_SOC(o)
Tq
Tq
RPHY_DATA(o)
/RPHY_EN(i)
D1
D2
D3
Figure 65. TUTOPIA MPHY Timing
ꢈꢈ
PMC [ PMC-SIERRA, INC ]
