PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
Figure 66 illustrates the receive ATM UTOPIA timing.
Tsu
Th
Tdc
Fc
RATM_CLK(i)
/RATM_EMPTY(i)
RATM_DATA(i)
RATM_SOC(i)
1
2
3
4
5
6
7
8
Tq
/RATM_EN(o)
Figure 66. Receive UTOPIA ATM Timing
Signals
Symbol
Parameter
Clock frequency
Min
Max
Unit
Fc
Tdc
Tsu
Th
RATM_CLK
RATM_CLK
33
55
MHz
%
Clock duty cycle
Clock setup
45
5
/RATM_EMPTY, RATM_DATA, RATM_SOC
/RATM_EMPTY, RATM_DATA, RATM_SOC
/RATM_EN
ns
Clock hold
1
ns
Tq
Clock-to-output delay
2
12
ns
6.4.2 RUTOPIA as the PHY Layer Device in Single-PHY (SPHY) Mode
The RUTOPIA block functions as a transmit UTOPIA block when in SPHY mode. The transmit
SPHY UTOPIA timing signals are compatible with the UTOPIA Level 1 cell-level hand-shaking
specification (refer to Appendix B, “References”, on page 203). Table 20 indicates the transmit
UTOPIA signal names and their corresponding UTOPIA designations. The device will not assert
TPHY_CLAV unless it can receive an entire cell. When ready, the device will accept data for any
cycle that /TPHY_EN is active. If the current cell will fill the internal FIFO, then TPHY_CLAV
will be deactivated the same cycle it is receiving the 49th byte of data. Figure 67 shows the data
input timing for the RUTOPIA block in SPHY mode. The timing parameters used in Figure 67
are defined in the table following the figure. Refer section 3.5 “Receive UTOPIA Interface Block
(RUTOPIA)” starting on page 44 for additional information.
Table 20. Transmit Signal Names and Corresponding UTOPIA Designations
Signal Name
UTOPIA Name
/TPHY_ADDR
TPHY_DATA
TPHY_SOC
TPHY_CLAV
/TPHY_EN
TxAddr
TxData
TxSOC
TxClav
TxEnb*
TxClk
TPHY_CLK
ꢀꢉꢀ
PMC [ PMC-SIERRA, INC ]
