PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
6.2 Receive Side Line Interface Timing
Figure 59, Figure 60, Figure 61 on page 96, and Figure 62 on page 96 show the receiver transmits
data to the lines for low-speed applications. These lines typically interface with the transmit input
portion of the corresponding framer. The AAL1gator II drives the same signaling data onto TL_
SIG during each frame of a multiframe. Data is output off the rising edge of TL_CLK, and TL_
FSYNC and TL_MSYNC are sampled using the falling edge of TL_CLK. The timing parameters
are explained in the tables following the figures.
Fc
Tsu
Tcp
Tcp
TL_CLK(i)
TL_FSYNC(i)
Th
TL_MSYNC(i)
TL_SIG(o)
Tq
TL_SER(o)
Figure 59. Receive Side Low-Speed Interface Bit Timing
Symbol
Parameter
Clock frequency
Signals
Min
Max
Unit
Fc
Tcp
Tsu
Th
TL_CLK
TL_CLK
15
MHz
ns
Clock pulse width
Clock setup
10
5
TL_MSYNC, TL_FSYNC
TL_MSYNC, TL_FSYNC
TL_SIG, TL_SER
ns
Clock hold
1
ns
Tq
Clock-to-output delay
2
14
ns
The format of signaling data on the TL_SIG output is dependent on the framer operating mode.
When operating in T1 mode, the AAL1gator II drives signaling only on the lower four bits of each
timeslot as shown in Table 15 on page 93 and Figure 60. In all cases, signaling data is driven on
the TL_SIG pin for all frames of each multiframe.
The rising edge of TL_FSYNC should occur only during the frame (F) bit of the T1 data stream.
The rising edge of TL_MSYNC should occur only during the F bit that starts each 12-frame (SF)
or 24-frame (ESF) multiframe. If a sync input occurs when it is not expected, the AAL1gator II
will resync to the new structure. The sync pulses do not have to be driven every frame or multi-
frame.
ꢈꢄ
PMC [ PMC-SIERRA, INC ]
