PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
RL_CLK(i)
RL_FSYNC(i)
RL_MSYNC(i)
TS31, FRAME 15
TS0, FRAME 0
TS1, FRAME 0
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RL_SER(i)
RL_SIG(i)
C
D
A
B
C
D
A
B
C
D
A
B
C
D
Figure 57. Transmit Side E1 Interface Frame Timing
Table 16. Signaling Format for E1 Mode
1234
5678
PCM Channel Number
XXXX ABCD
0
1
...
30
31
X
X
X
X
X
0
1
...
30
31
In UDF-HS mode there is no structure and the data is sampled using RL_CLK(0) as shown in
Figure 58.
Th
Fc
Tsu
Tcp
Tcp
RL_CLK(i)
RL_SER(i)
Figure 58. Transmit Side High-Speed Interface Timing
Parameter Signals Min
Symbol
Max
45
Unit
Fc
Tcp
Tsu
Th
Clock frequency
Clock pulse width
Clock setup
RL_CLK(0)
RL_CLK(0)
RL_SER(0)
RL_SER(0)
MHz
ns
10
5
ns
Clock hold
2
ns
ꢈꢃ
PMC [ PMC-SIERRA, INC ]
