PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
When operating in T1 mode, the AAL1gator II expects signaling only on the lower four bits of
each timeslot as shown in Table 15 and Figure 56. Signaling data is accepted from the RL_SIG
pin only during the last frame of each multiframe.
The rising edge of RL_FSYNC should only occur during the frame (F) bit of the T1 data stream.
The rising edge of RL_MSYNC should only occur during the F bit which starts each 12-frame
(SF) or 24-frame (ESF) multiframe. If a sync input occurs when it is not expected, the
AAL1gator II will resync to the new framing. The sync pulses do not have to be driven every
frame or multiframe.
RL_CLK(i)
RL_FSYNC(i)*
RL_MSYNC(i)
CHAN 24, FRAME 24
CHAN 1, FRAME 1
RL_SER(i)
RL_SIG(i)
7
8
1
2
3
4
5
6
7
8
F
1
2
3
4
5
6
7
8
C
D
A
B
C
D
A
B
C
D
*T1 mode
Figure 56. Transmit Side T1 Interface Frame Timing
Table 15. Signaling Format for T1 Mode
1234
5678
PCM Channel Number
XXXX ABCD
1
2
...
23
24
X
X
X
X
X
1
2
...
23
24
In E1 mode, signaling data is expected only on the lower four bits of each timeslot as shown in
Table 16 on page 94. Signaling data is only accepted from the RL_SIG pin in the last frame of
each multiframe. The AAL1gator II treats all 32 timeslots the same. Although E1 data streams
contain 30 timeslots of channel data and 2 timeslots of control, data and signaling for all 32
timeslots are stored in memory.
The rising edge of RL_FSYNC should only occur during the first bit of each frame of the E1 data
stream. The rising edge of RL_MSYNC should only occur during the first bit of each 16 frame
multiframe. If E1_WITH_T1_SIG is set, then the rising edge of RL_MSYNC should only occur
during the first bit of each 24 frame multiframe. If a sync input occurs when it is not expected, the
AAL1gator II will resync to the new structure. The sync pulses do not have to be driven every
frame or multiframe.
ꢈꢂ
PMC [ PMC-SIERRA, INC ]
