PM73121ꢀAAL1gator II
Data Sheet
PMC-Sierra, Inc.
PMC-980620
,VVXHꢀꢁ
AAL1 SAR Processor
6 TIMING DIAGRAMS
6.1 Transmit Side Line Interface Timing
Figure 55, Figure 56 on page 93, Figure 57 on page 94, and Figure 58 on page 94 show how the
transmitter receives data from the line interface. These lines typically interface with the receive
output portion of the corresponding framer. The timing parameters are explained in the table fol-
lowing Figure 55.
RL_FSYNC and RL_MSYNC are used in structured modes to align the frame and multiframe of
the incoming data. These inputs are ignored in unstructured modes.
The AAL1gator II expects all signals to be asserted from the rising edge of RL_CLK, and samples
all signals on the falling edge of RL_CLK, as shown in the following figures.
Th
Fc
Tsu
Tcp
Tcp
RL_CLK(i)
RL_FSYNC(i)
RL_MSYNC(i)
RL_SIG(i)
RL_SER(i)
Figure 55. Transmit Side Interface Bit Timing
Symbol
Parameter
Clock frequency
Signals
Min
Max
15
Unit
Fc
RL_CLK
RL_CLK
MHz
ns
Tcp
Tsu
Clock pulse width
Clock setup
10
5
RL_MSYNC, RL_FSYNC,
RL_SIG, RL_SER
ns
Th
Th
Clock hold
Clock hold
RL_MSYNC, RL_FSYNC,
RL_SIG
1
2
ns
ns
RL_SER
ꢈꢁ
PMC [ PMC-SIERRA, INC ]
