PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Options Register is set to logic 1), or the Master Interrupt Source Register, to
determine when to read the Data Register. The RXDMASIG bit in the Datalink
Options Register should be set to logic 1. RDLINTE of the same register should
be set to logic 1 if the INTB output is used as the interrupt source. The processor
interrupt service routine should process the data in the following order:
1. Wait for an interrupt originating from the RFDL. Once the interrupt is set, then
proceed to step 2.
2. Read the RFDL Data Register.
3. Read the RFDL Status Register to check for the following:
a) If OVR=1, then discard the current frame and go to step 1.
ELSE
b) If FLG=0 (i.e. an abort has been received) and the link state was active,
then set the link state to inactive, discard the current frame, and go to step 1.
c) If FLG=1 and the link state was inactive, then set the link state to active,
discard the last data byte, and go to step 1.
ELSE
d) Save the last data byte read.
e) If EOM=1, then read the CRC and NVB[2:0] bits of the RFDL Status
Register to process the frame properly.
f) If FE=0, then go to step 2, else go to step 1.
DMA-Controlled Mode
The RFDL can also be used with a DMA controller to process the frame data. In
the DMA controlled mode, the RDLINT output of the RFDL is used as a DMA
request input to the DMA controller, and the RDLEOM output is used as an
interrupt to the processor to allow handling of exceptions and as an indication of
when to process a frame. The RXDMASIG bit of the Datalink Options Register
should be set to logic 1.
The RDLINT output of the RFDL is connected through a gate to the DMA
request input of the DMA controller to optionally inhibit the DMA request if the
RDLEOM output is high. The DMA controller reads the data bytes from the
RFDL whenever the RDLINT output is high. When the current byte read from the
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