PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
Polled Mode
If the XFDL data transfer is operating in the polled mode (TXDMASIG, TDLINTE,
and TDLUDRE bits in the Datalink Options Register are set to logic 0), then a
timer periodically starts up a service routine, which should process data as
follows:
1. Read the XFDL Interrupt Status Register and poll the UDR and INT bits.
2. If UDR=1, then clear the UDR bit in the XFDL Interrupt Status Register to
logic 0, and restart the current frame. Go to step 1.
3. If INT=1, then:
a) If there is still data to send, then write the next data byte to the XFDL
Transmit Data Register;
b) If all bytes in the frame have been sent, then set the EOM bit in the XFDL
Configuration Register to logic 1.
4. If EOM bit was set to logic 1 in step 3b, then:
a) Read the XFDL Interrupt Status Register and check the UDR bit.
b) If UDR=1 then reset the UDR bit in the XFDL Interrupt Status Register
and the EOM bit in the XFDL Configuration Register to logic 0, and retransmit
the last frame.
5. Go to step 1.
Interrupt Mode
In the case of interrupt driven data transfer, the TDLINT output is connected to
the interrupt input of the processor, and the interrupt service routine should
process the data exactly as described above for the polled mode. The INTE bit in
the XFDL Configuration Register must be set to logic 1. Alternately, the INTB
output can be connected to the interrupt input of the processor if the TDLINTE bit
of the Datalink Options Register is set to logic 1. If this mode is used, additional
polling of the Master Interrupt Source register must be performed to identify the
cause of the interrupt before the initiating the interrupt service routine.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
198
PMC [ PMC-SIERRA, INC ]
