PM6341 E1XC
DATA SHEET
PMC-910419
ISSUE 8
E1 FRAMER/TRANSCEIVER
DMA-Controlled Mode
The XFDL can also be used with a DMA controller to process the frame data. In
this case, the TDLUDR output is connected to the processor interrupt input. The
TDLINT output of the XFDL is connected to the DMA request input of the DMA
controller. The INTE bit in the XFDL Configuration Register must be set to logic 1
before enabling the XFDL. The DMA controller writes a data byte to the XFDL
whenever the TDLINT output is high. If there is a problem during transmission
and an underrun condition occurs, then the TDLUDR output goes high and the
processor is interrupted. The processor can then halt the DMA controller, reset
the UDR bit in the XFDL Interrupt Status Register, reset the frame data pointers,
and restart the DMA controller to resend the data frame. After the message
transmission is completed, the DMA controller must initiate a write to set the
EOM bit in the XFDL Configuration Register and then verify that TDLUDR is not
set prior to setting EOM.
14.3 Using the Internal FDL Receiver
On power up of the E1XC, the RFDL should be disabled by setting the EN bit in
the Configuration Register to logic 0. The RFDL Interrupt Control/Status Register
should then be initialized to select the FIFO buffer fill level at which time an
interrupt will be generated.
After the Interrupt Control/Status Register has been written to, the RFDL can be
enabled at any time by setting the EN bit in the Configuration Register to logic 1.
When the RFDL is enabled, it will assume that the link status is idle (all ones)
and immediately begin searching for flags. When the first flag is found, an
interrupt will be generated (if enabled), and the byte received before the first flag
was detected will be written into the FIFO buffer. Because the FLG and EOM
bits are passed through the buffer, this dummy write allows the RFDL Status
Register to accurately reflect the current state of the data link. A RFDL Status
Register read after a RFDL Data Register read of the dummy byte will return
EOM as logic 1 and FLG as logic 1. The first interrupt and data byte read after
the RFDL is enabled (or TR bit set to logic 1) is an indication of the link status,
and the data byte should therefore be discarded. It is up to the controlling
processor to keep track of the link state as idle (all ones or bit-oriented
messages active) or active (flags received).
The RFDL can be used in a polled, interrupt driven, or DMA controlled mode for
the transfer of frame data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
