PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
respectively. When TDPINV is set to logic 1, the TDP/TDD output is inverted.
When TDPINV is set to logic 0, the TDP/TDD output is not inverted. When
TDNINV is set to logic 1, the TDN/TFLG output is inverted. When TDNINV is
set to logic 0, the TDN/TFLG output is not inverted.
TUNI:
The TUNI bit enables the transmit interface to generate uni-polar digital
outputs on the TDP/TDD and TDN/TFLG multifunction pins. When TUNI is
set to logic 1, the TDP/TDD and TDN/TFLG multifunction pins become the
unipolar outputs TDD and TFLG, updated on the selected TCLKO edge.
When TUNI is set to logic 0, the TDP/TDD and TDN/TFLG multifunction pins
become the bipolar outputs TDP and TDN, also updated on the selected
TCLKO edge. When the TUNI bit is set to logic 1 (unipolar mode), the analog
transmit data outputs, TAP and TAN, from the XPLS block cannot be used.
FIFOFULL:
The FIFOFULL bit determines the indication given on the TFLG output pin.
When FIFOFULL is set to logic 1, the TFLG output indicates when the Digital
Jitter Attenuator's FIFO is within 4 bit positions of becoming full. When
FIFOFULL is set to logic 0, the TFLG output indicates when the Digital Jitter
Attenuator's FIFO is within 4 bit positions of becoming empty.
TRISE:
The TRISE bit configures the interface to update the multifunction outputs on
the rising edge of TCLKO. When TRISE is set to logic 1, the interface is
enabled to update the TDP/TDD and TDN/TFLG output pins on the rising
TCLKO edge. When TRISE is set to logic 0, the interface is enabled to
update the outputs on the falling TCLKO edge.
TRZ:
The TRZ bit configures the interface to transmit bipolar return-to-zero
formatted waveforms. When TRZ is set to logic 1, the interface is enabled to
generate the TDP and TDN output signals as RZ waveforms with duration
equal to half the TCLKO period. When TRZ is set to logic 0, the interface is
enabled to generate the TDP and TDN output signals as NRZ waveforms with
duration equal to the TCLKO period, updated on the selected edge of TCLKO.
The TRZ bit can only be used when TUNI and TRISE are set to logic 0.
When the system is reset, the contents of the register are set to logic 0, enabling
the Transmit Interface to output NRZ formatted positive and negative pulse data
on the TDP and TDN outputs, updated on the falling TCLKO edge.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
74
PMC [ PMC-SIERRA, INC ]
