PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 04H:T1XCTransmit DS1 Interface Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FIFOBYP
TAISEN
TDNINV
TDPINV
TUNI
0
0
0
0
0
0
0
0
FIFOFULL
TRISE
TRZ
This register enables the Transmit DS1 Interface to generate the required digital
output waveform format.
FIFOBYP:
The FIFOBYP bit enables the transmit bi-polar input signals to DJAT to be
bypassed around the FIFO to the bi-polar outputs. When jitter attenuation is
not being used, and the XPLS pulse driver is being driven with a "jitter-free"
12.352MHz clock on TCLKI, the DJAT FIFO can be bypassed to reduce the
delay through the transmitter section by typically 24 bits. NOTE: under this
condition, the BTCLK signal must be synchronous to the TCLKI. When
FIFOBYP is set to logic 1, the bi-polar inputs to DJAT are routed around the
FIFO and directly into XPLS. When FIFOBYP is set to logic 0, the bi-polar
transmit data passes through the DJAT FIFO.
TAISEN:
The TAISEN bit enables the interface to generate an unframed all-ones AIS
alarm on the TDP/TDD and TDN/TFLG multifunction pins. When TAISEN is
set to logic 1 and TUNI is set to logic 0, the bi-polar TDP and TDN outputs are
forced to pulse alternately, creating an all-ones signal; when TAISEN and
TUNI are both set to logic 1, the uni-polar TDD output is forced to all-ones.
When TAISEN is set to logic 0, the TDP/TDD and TDN/TFLG multifunction
outputs operate normally.The transition to transmitting AIS on the TDP and
TDN outputs is done in such a way as to not introduce any bi-polar violations.
TDPINV,TDNINV:
The TDPINV and TDNINV bits enable the DS-1 Transmit Interface to logically
invert the signals output on the TDP/TDD and TDN/TFLG multifunction pins,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
73
PMC [ PMC-SIERRA, INC ]
