PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 05H:T1XCTransmit Backplane Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
X
0
0
0
0
0
Unused
R/W
R/W
R/W
R/W
R/W
ABXXEN
BTXCLK
BTX2M
BTX2RAIL
BTXSFP
This register allows software to configure the Transmit backplane interface format
of the T1XC.
ABXXEN:
The ABXXEN bit selects the format of the BTSIG transmit signalling input
signal. When ABXXEN is set to logic 1, BTSIG is expected to contain only
the A and B signalling bits in the upper two bit positions of the lower nibble of
each channel (i.e. ABXX), with the lower two bit positions being "Don't Cares".
When ABXXEN is set to logic 0, BTSIG is expected to contain all four
signalling bit in the lower nibble of each channel (i.e. ABCD), or it is expected
to contain the A and B bits duplicated in the lower nibble (i.e. ABAB).
BTXCLK:
The BTXCLK bit selects the source of the XBAS transmit clock input signal.
When BTXCLK is set to logic 1, the XBAS transmit clock is driven with the
1.544MHz recovered PCM output clock (RCLKO) from the receiver section.
When BTXCLK is set to logic 0, the XBAS transmit clock is driven with the
1.544MHz backplane transmit clock (BTCLK), or the internal "gapped" clock
derived from the 2.048MHz BTCLK. Note that this bit must be set to logic 1
when Line Loopback is enabled.
BTX2M:
The BTX2M bit selects the 2.048 MHz data rate and format of the backplane
transmit data and frame alignment signals. When BTX2M is set to logic 1, the
clock rate on the BTCLK input is expected to be 2.048 MHz, and the data
stream on BTPCM and BTSIG is expected to be formatted as 1 byte of "filler"
followed by 3 bytes of channel data, repeated 8 times. When BTX2M is set to
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
75
PMC [ PMC-SIERRA, INC ]
