PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
event causes an interrupt on both the EOM and INT RFDL interrupt outputs.
See the Operation section for further details on using the RFDL.
TDLINTE:
The TDLINTE bit enables the XFDL request for service interrupt to also
generate an interrupt on the microprocessor interrupt, INTB.This allows a
single microprocessor to service the XFDL without needing to interface to the
DMA control signals. When TDLINTE is set to logic 1, an request for service
interrupt event in the XFDL (which is visible on the TDLINT output pin when
TXDMASIG is logic 1 and TXDCHAN is logic 0) also causes and interrupt to
be generated on the INTB output. When TDLINTE is set to logic 0, an
interrupt event in the XFDL does not cause an interrupt on INTB.
TDLUDRE:
The TDLUDRE bit enables the XFDL transmit data underrun interrupt to also
generate an interrupt on the microprocessor interrupt, INTB.This allows a
single microprocessor to service the XFDL without needing to interface to the
DMA control signals. When TDLUDRE is set to logic 1, an underrun event
causing an interrupt in the XFDL (which is visible on the TDLUDR output pin
when TXDMASIG is logic 1 and TXDCHAN is logic 0) also causes and
interrupt to be generated on the INTB output. When TDLUDRE is set to logic
0, an underrun event in the XFDL does not cause an interrupt on INTB.
Upon reset of the T1XC, these bits are cleared to zero.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
70
PMC [ PMC-SIERRA, INC ]
