PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
SDN/RDN/RLCV, respectively. When RDPINV is set to logic 1, the interface
inverts the signal on the RDP/RDD input. When RDPINV is set to logic 0, the
interface passes the RDP/RDD signal unaltered. When RDNINV is set to logic
1, the interface inverts the signal on the RDN/RLCV input. When RDNINV is
set to logic 0, the interface passes the RDN/RLCV signal unaltered.
RUNI:
The RUNI bit enables the interface to receive uni-polar digital data and line
code violation indications on the multifunction pins SDP/RDP/RDD and
SDN/RDN/RLCV. When RUNI is set to logic 1, the SDP/RDP/RDD and
SDN/RDN/RLCV multifunction pins become the data and line code violation
inputs, RDD and RLCV, sampled on the selected RCLKI edge. When RUNI is
set to logic 0, the SDP/RDP/RDD and SDN/RDN/RLCV multifunction pins
become the positive and negative pulse inputs, RDP and RDN, sampled on
the selected RCLKI edge.
RFALL:
The RFALL bit enables the DS-1 Receive Interface to sample the
multifunction pins on the falling RCLKI edge. When RFALL is set to logic 1,
the interface is enabled to sample either the RDD and RLCV inputs, or the
RDP and RDN inputs, on the falling RCLKI edge. When RFALL is set to logic
0, the interface is enabled to sample the inputs on the rising RCLKI edge.
RRZ:
The RRZ bit configures the interface to receive return-to-zero formatted
waveforms. When RRZ is set to logic 1, the interface is configured to pass the
signals on the RDP and RDN inputs unaltered directly into the CDRC . The
RCLKI input is ignored. When RRZ is set to logic 0, the interface is
configured to sample either the RDD input or the RDP and RDN inputs on the
RCLKI edge specified by the RFALL bit and generate an internal RZ
representation of these inputs with duration equal to half the RCLKI period.
The internally-generated RZ signals are then passed on to CDRC. The RRZ
bit is only valid when RUNI is set to logic 0.
When the system is reset, the contents of the register are set to logic 0, enabling
the analog Receive Slicer Interface to handle the incoming DSX-1 signal.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
72
PMC [ PMC-SIERRA, INC ]
