PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
FBITBYP:
The FBITBYP bit allows the frame synchronization bit in the input data
stream, BTPCM, to bypass the generation through the XBAS and be re-
inserted into the appropriate position in the digital output stream. When
FBITBYP is set to logic 1, the input frame synchronization bit is re-inserted
into the output data stream. When FBITBYP is set to logic 0, the XBAS is
allowed to generate the output frame synchronization bits.
CRCBYP:
The CRCBYP bit allows the framing bit corresponding to the CRC-6 bit
position in the input data stream, BTPCM, to bypass the generation through
the XBAS and be re-inserted into the appropriate position in the digital
output stream. When CRCBYP is set to logic 1, the input CRC-6 bit is re-
inserted into the output data stream. When CRCBYP is set to logic 0, the
XBAS is allowed to generate the output CRC-6 bits.
FDLBYP:
The FDLBYP bit allows the framing bit corresponding to the facility data link
bit position in the input data stream, BTPCM, to bypass the generation
through the XBAS and be re-inserted into the appropriate position in the
digital output stream. When FDLBYP is set to logic 1, the input FDL bit is re-
inserted into the output data stream. When FDLBYP is set to logic 0, the
XBAS is allowed to generate the output FDL bit.
Upon reset of the T1XC, these bits are cleared to zero.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
78
PMC [ PMC-SIERRA, INC ]
