PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 06H:T1XCTransmit Framing and Bypass Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
SIGAEN
TXSIGA
FDIS
X
X
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
FBITBYP
CRCBYP
FDLBYP
This register allows software to configure the bypass options of the transmitter,
the use and location of the Signalling Alignment block, and controls the global
transmit framing disable.
SIGAEN:
The SIGAEN bit enables the operation of the signalling aligner (SIGA) to
ensure superframe alignment between the backplane and either the receive
or transmit DS-1 streams. When set to logic 1, the SIGA is inserted into the
signalling bit data path either after the SIGX or before the XBAS , as
selected by the TXSIGA register bit. When the signalling aligner is used, the
backplane frame alignment indication must also be changed to indicate
superframe alignment for either the receive or transmit backplane, based on
the value of TXSIGA. When SIGAEN is set to logic 0, the SIGA is removed
from the circuit and the TXSIGA bit is ignored.
TXSIGA:
The TXSIGA bit selects the location of the signalling aligner. When set to
logic 1, the SIGA is inserted into the signalling bit data path before the
XBAS. When set to logic 0, the SIGA is inserted into the data path after the
SIGX.
FDIS:
The FDIS bit allows the framing generation through the XBAS to be disabled
and the transmit data to pass through the XBAS unchanged. When FDIS is
set to logic 1, XBAS is disabled from generating framing. When FDIS is set to
logic 0, XBAS is enabled to generate and insert the framing into the transmit
data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
77
PMC [ PMC-SIERRA, INC ]
