PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 03H:T1XC Receive DS1 Interface Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
SDOEN
RDIEN
RDNINV
RDPINV
RUNI
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RFALL
RRZ
This register enables the Receive DS1 Interface to handle the various input
waveform formats.
SDOEN:
The SDOEN bit enables the sliced positive and negative pulses from the
analog receive slicer to be visible on the SDP and SDN pins when the Analog
DSX-1 Receive Slicer is active. When SDOEN is set to logic 1, the
multifunction pins SDP/RDP/RDD and SDN/RDN/RLCV become the sliced
positive and negative pulse outputs, SDP and SDN. Pulses will be seen on
the SDP and SDN outputs if RSLC is powered up. When SDOEN is set to
logic 0, the multifunction pins SDP/RDP/RDD and SDN/RDN/RLCV become
the digital inputs, RDP/RDD and RDN/RLCV.The function of the digital inputs
is determined by the RUNI bit.
RDIEN:
The RDIEN bit enables data received on the digital inputs, RDP/RDD and
RDN/RLCV, to be used internally instead of the outputs from the Analog DSX-
1 Receive Slicer. When RDIEN is set to logic 1 and SDOEN is set to logic 0,
digital data input on the multifunction pins RDP/RDD and RDN/RLCV are
handled in accordance with the remaining bit setting in this register and the
resulting signals are used internally to drive the clock and data recovery
block. When RDIEN is set to logic 0, the output signals from the analog
RSLC are used internally to drive the CDRC block.
RDPINV,RDNINV:
The RDPINV and RDNINV bits enable the DS-1 Receive Interface to logically
invert the signals received on multifunction pins SDP/RDP/RDD and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
71
PMC [ PMC-SIERRA, INC ]
