PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
TXDMASIG:
The TXDMASIG bit selects the internal HDLC transmitter (XFDL) request for
service interrupt (INT) and data underrun (UDR) signals to be output on the
TDLINT and TDLUDR pins when the TXDCHAN bit is logic 0. When
TXDMASIG is set to logic 1, the TDLINT and TDLUDR output pins can be
used by a DMA controller to service the datalink. When TXDMASIG is set to
logic 0, the XFDL INT and UDR signals are no longer available to a DMA
controller; the signals on TDLINT and TDLUDR become the serial datalink
data input and clock, TDLSIG and TDLCLK. In this mode an external
controller is responsible for formatting the data stream presented on the
TDLSIG input to correspond to the facility datalink in ESF, the R-bit value of
the sync word in T1DM, or the Fs framing bits in SLC®96. When TXDCHAN
is set to logic 1, the TXDMASIG bit has no effect.
TXDCHAN:
The TXDCHAN bit selects whether the Primary Rate D-Channel is inserted
into channel 24 of each frame via the TDLSIG input, or whether the
TDLINT/TDLSIG and TDLUDR/TDLCLK pins operate as defined by the
TXDMASIG bit. When TXDCHAN is set to logic 1, the D-Channel data is
expected on TDLSIG, sampled on the rising edge of a burst clock provided on
TDLCLK. When TXDCHAN is set to logic 0, the TDLINT/TDLSIG and
TDLUDR/TDLCLK pins contain the signals selected by the TXDMASIG bit.
RDLINTE:
The RDLINTE bit enables the RFDL received-data interrupt to also generate
an interrupt on the microprocessor interrupt, INTB.This allows a single
microprocessor to service the RFDL without needing to interface to the DMA
control signals. When RDLINTE is set to logic 1, an event causing an
interrupt in the RFDL (which is visible on the RDLINT output pin when
RXDMASIG is logic 1 and RXDCHAN is logic 0) also causes an interrupt to
be generated on the INTB output. When RDLINTE is set to logic 0, an
interrupt event in the RFDL does not cause an interrupt on INTB.
RDLEOME:
The RDLEOME bit enables the RFDL end-of-message interrupt to also
generate an interrupt on the microprocessor interrupt, INTB.This allows a
single microprocessor to service the RFDL without needing to interface to the
DMA control signals. When RDLEOME is set to logic 1, an end-of-message
event causing an EOM interrupt in the RFDL (which is visible on the
RDLEOM output pin when RXDMASIG is logic 1 and RXDCHAN is logic 0)
also causes an interrupt to be generated on the INTB output. When
RDLEOME is set to logic 0, an EOM interrupt event in the RFDL does not
cause an interrupt on INTB. NOTE: within the RFDL, an end-of-message
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
69
PMC [ PMC-SIERRA, INC ]
