PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 02H:T1XC Datalink Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RXDMASIG
RXDCHAN
TXDMASIG
TXDCHAN
RDLINTE
0
0
0
0
0
0
0
0
RDLEOME
TDLINTE
TDLUDRE
This register allows software to configure the datalink options of the T1XC.
RXDMASIG:
The RXDMASIG bit selects the internal HDLC receiver (RFDL) data-received
interrupt (INT) and end-of-message (EOM) signals to be output on the
RDLINT and RDLEOM pins when the RXDCHAN bit is logic 0. When
RXDMASIG is set to logic 1, the RDLINT and RDLEOM output pins can be
used by a DMA controller to process the datalink. When RXDMASIG is set to
logic 0, the RFDL INT and EOM signals are no longer available to a DMA
controller; the signals on RDLINT and RDLEOM become the extracted
datalink data and clock, RDLSIG and RDLCLK. In this mode, the data stream
available on the RDLSIG output corresponds to the extracted facility datalink
in ESF, the extracted R-bit value of the sync word in T1DM, or the extracted
Fs framing bits in SLC®96. When RXDCHAN is set to logic 1, the RXDMASIG
bit has no effect.
RXDCHAN:
The RXDCHAN bit selects whether the Primary Rate D-Channel is extracted
and made available on the RDLSIG output, or whether the RDLINT/RDLSIG
and RDLEOM/RDLCLK pins operate as defined by the RXDMASIG bit. When
RXDCHAN is set to logic 1, the D-Channel data (channel 24 of every frame)
is output on RDLSIG and a burst clock is output on RDLCLK. When
RXDCHAN is set to logic 0, the RDLINT/RDLSIG and RDLEOM/RDLCLK
pins contain the signals selected by the RXDMASIG bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
68
PMC [ PMC-SIERRA, INC ]
