PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 01H:T1XC Receive Backplane Options
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
ALTFDL
X
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RXDMAGAT
BRX2M
BRX2RAIL
BRXSFP
ALTBRFP
RXMTKC
This register allows software to configure the Receive backplane interface format
of the T1XC.
ALTFDL:
The ALTFDL bit enables the framing bit position on the backplane PCM
output to contain a copy of the FDL bit. When ALTFDL is set to logic 1, each
M-bit value in the ESF-formatted stream is duplicated and replaces the
subsequent CRC bit or F-bit in the output signal stream on BRPCM. When
ALTFDL is set to logic 0, the output BRPCM stream contains the received M,
CRC, or F bits in the framing bit position. Note that this function is only valid
for ESF-formatted streams, ALTFDL should be set to logic 0 when other
framing formats are being received.
RXDMAGAT:
The RXDMAGAT bit selects the gating of the RDLINT output with the
RDLEOM output when the internal HDLC receiver is used with DMA. When
RXDMAGAT is set to logic 1, the RDLINT DMA output is gated with the
RDLEOM output so that RDLINT is forced to logic 0 when RDLEOM is logic
1. When RXDMAGAT is set to logic 0, the RDLINT and RDLEOM outputs
operate independently.
BRX2M:
The BRX2M bit selects the 2.048 MHz data rate and format of the backplane
data and frame alignment signals. When BRX2M is set to logic 1, the clock
rate on the BRCLK input is expected to be 2.048MHz, and the data stream on
BRPCM is output as 1 byte of "filler" followed by 3 bytes of channel data,
repeated 8 times. When BRX2M is set to logic 0, the backplane data rate and
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
66
PMC [ PMC-SIERRA, INC ]
