STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
Recovered T1 and E1 Clocks
RECVCLK1
Output D22
Recovered Clock 1 (RECVCLK1). This clock output is
a recovered and de-jittered clock from any one of the
28 T1 framers or 21 E1 framers.
RECVCLK2
Output C22
Recovered Clock 2 (RECVCLK2). This clock output is
a recovered and de-jittered clock from any one of the
28 T1 framers or 21 E1 framers.
Scaleable Bandwidth Interconnect Interface
SREFCLK
Input B7
System Reference Clock (SREFCLK). This system
reference clock is a nominal 19.44MHz +/-50ppm 50%
duty cycle clock. This clock is common to both the add
and drop sides of the SBI bus.
System C1 Frame Pulse (SC1FP). The System C1
Frame Pulse is used to synchronize devices interfacing
to the SBI bus. This signal is common to both the add
and drop sides of the system SBI bus.
SC1FP
I/O
A6
By default, SC1FP is an input. The TECT3 can
alternatively be configured to generate this frame pulse
- as an output on SC1FP - for use by all other devices
connected to the same SBI bus. Note that all devices
interconnected via an SBI interface must be
synchronized to an SC1FP signal from a single
common source.
As an input, SC1FP is sampled on the rising edge of
SREFCLK. It normally indicates SBI mutiframe
alignment, and thus should be asserted for a single
SREFCLK cycle every 9720 SREFCLK cycles or some
multiple thereof (i.e. every 9720*N SREFCLK cycles,
where N is a positive integer). In synchronous SBI
mode, however, SC1FP is used to indicate T1
signaling multiframe alignment, and thus should be
asserted for a single SREFCLK cycle once every 12
SBI mutiframes (48 T1 frames or 116640 SREFCLK
cycles).
As an output, SC1FP is generated on the rising edge
PROPRIETARY AND CONFIDENTIAL
42
PMC [ PMC-SIERRA, INC ]
