STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
of SREFCLK. It normally indicates SBI mutiframe
alignment by pulsing high once every 9720 SREFCLK
cycles. In synchronous SBI mode, however, SC1FP is
used to indicate T1 signaling multiframe alignment by
pulsing once every 12 SBI mutiframes (48 T1 frames
or 116640 SREFCLK cycles).
SADATA[0]
SADATA[1]
SADATA[2]
SADATA[3]
SADATA[4]
SADATA[5]
SADATA[6]
SADATA[7]
Input D6
System Add Bus Data (SADATA[7:0]). The System
add data bus is a time division multiplexed bus which
carries the T1 and DS3 tributary data is byte serial
format over the SBI bus structure. This device only
monitors the add data bus during the timeslots
assigned to this device.
C7
D4
B6
A5
B5
A4
C5
SADATA[7:0] is sampled on the rising edge of
SREFCLK.
This bus shares pins with
ED[15,16,19,20,23,24,27,28].
SADP
SAPL
Input A2
Input B4
System Add Bus Data Parity (SADP). The system
add bus signal carries the even or odd parity for the
add bus signals SADATA[7:0], SAPL and SAV5. The
TECT3 monitors parity across all links on the add bus.
SADP is sampled on the rising edge of SREFCLK.
This signal shares a pin with signal ED[8].
System Add Bus Payload Active (SAPL). The add
bus payload active signal indicates valid data within the
SBI bus structure. This signal must be high during all
octets making up a tributary. This signal goes high
during the V3 or H3 octet of a tributary to indicate
negative timing adjustments between the tributary rate
and the fixed SBI bus structure. This signal goes low
during the octet after the V3 or H3 octet of a tributary
to indicate positive timing adjustments between the
tributary rate and the fixed SBI bus structure.
The TECT3 only monitors the add bus payload active
signal during the tributary timeslots assigned to this
device.
SAPL is sampled on the rising edge of SREFCLK.
PROPRIETARY AND CONFIDENTIAL
43
PMC [ PMC-SIERRA, INC ]
