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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Pin Name  
Type Pin Function  
No.  
CASED[4]  
CASED[5]  
CASED[6]  
CASED[7]  
M22 DS0s or E1 timeslots. Each CASED[x] signal carries  
M1 CAS for four complete T1s or E1s formatted according  
E22 to the H-MVIP standard. CASED[x] carries the  
L2 corresponding CAS values of the channel data carried  
in MVED[x].  
CASED[x] is aligned to the common H-MVIP  
16.384Mb/s clock, CMV8MCLK, frame pulse clock,  
CMVFPC, and frame pulse, CMVFPB. CASED[x] is  
sampled on every second rising or falling edge of  
CMV8MCLK as fixed by the common H-MVIP frame  
pulse clock, CMVFPC. The sampling edge of  
CMV8MCLK is selected via the CMVEDE bit in the  
Master Common Ingress Serial and H-MVIP Interface  
Configuration register.  
CASED[1:7] shares the same pins as  
ED[2,6,10,14,18,22,26].  
CCSED  
Input P1  
Common Channel Signaling Egress Data (CCSED).  
In T1 mode CCSED carries the 28 common channel  
signaling channels to be transmitted in each of the 28  
T1s. In E1 mode CCSED carries up to 3 timeslots  
(15,16, 31) to be transmitted in each of the 21 E1s.  
CCSED is formatted according to the H-MVIP  
standard.  
CCSED is aligned to the common H-MVIP 16.384Mb/s  
clock, CMV8MCLK, frame pulse clock, CMVFPC, and  
frame pulse, CMVFPB. CCSED is sampled on every  
second rising or falling edge of CMV8MCLK as fixed  
by the common H-MVIP frame pulse clock, CMVFPC.  
The sampling edge of CMV8MCLK is selected via the  
CMVEDE bit in the Master Common Ingress Serial and  
H-MVIP Interface Configuration register.  
PROPRIETARY AND CONFIDENTIAL  
41  
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