STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
Configuration register.
CASID[1:7] shares the same pins as
ID[2,6,10,14,18,22,26].
CCSID
Output T4
Common Channel Signaling Ingress Data (CCSID).
In T1 mode CCSID carries the 28 common channel
signaling channels extracted from each of the 28 T1s.
In E1 mode CCSID carries up to 3 timeslots (15,16,
31) from each of the 21 E1s. CCSID is formatted
according to the H-MVIP standard.
CCSID is aligned to the common H-MVIP 16.384Mb/s
clock, CMV8MCLK, frame pulse clock, CMVFPC, and
frame pulse, CMVFPB. CCSID is updated on every
second rising or falling edge of CMV8MCLK as fixed
by the common H-MVIP frame pulse clock, CMVFPC.
The updating edge of CMV8MCLK is selected via the
CMVIDE bit in the Master Common Ingress Serial and
H-MVIP Interface Configuration register.
MVED[1]
MVED[2]
MVED[3]
MVED[4]
MVED[5]
MVED[6]
MVED[7]
Input AB4
MVIP Egress Data (MVED[1:7]). The egress data
streams to be transmitted are input on these pins.
Each MVED[x] signal carries the channels of four
complete T1s formatted according to the H-MVIP
standard. MVED[x] carries the egress data equivalent
to ED[(4x-3):(4x)].
MVID[x] is aligned to the common H-MVIP 16.384Mb/s
clock, CMV8MCLK, frame pulse clock, CMVFPC, and
frame pulse, CMVFPB. MVID[x] is sampled on every
second rising or falling edge of CMV8MCLK as fixed
by the common H-MVIP frame pulse clock, CMVFPC.
The sampling edge of CMV8MCLK is selected via the
CMVEDE bit in the Master Common Ingress Serial and
H-MVIP Interface Configuration register.
N21
T2
N19
P2
C20
L1
In E1 mode only MVED[1:6] are used.
MVED[1:7] shares the same pins as
ED[1,5,9,13,17,21,25].
CASED[1]
CASED[2]
CASED[3]
Input AA3
N22
Channel Associated Signaling Egress Data
(CASED[1:7]). CASED[x] carries the channel
associated signaling stream to be transmitted in the T1
R4
PROPRIETARY AND CONFIDENTIAL
40
PMC [ PMC-SIERRA, INC ]
