Hot Plug Support
PLX Technology, Inc.
Figure 9-1 illustrates the timing sequence with the Power Controller Present bit (offset 7Ch[1]) set to 1.
This timing sequence occurs at system power-up, or when a slot is being powered up by the user.
If HP_MRLx# is enabled but not asserted to power-up the slot immediately after reset, HP_MRLx# can
be asserted at runtime to start the slot power-up sequence, provided the Power Controller Present and
MRL Sensor Present bits are set (offset 7Ch[2:1]=11b, either by default values when the serial
EEPROM is not present or blank, or by programming the serial EEPROM to set these bits), and the
Power Controller Control bit is cleared (offset 80h[10]=0, either by the programmed serial EEPROM or
by software). Power-up sequencing at runtime is controlled by software clearing the Power Controller
Control bit after HP_MRLx# assertion causes an interrupt, if enabled [the Slot Control register Hot
Plug Interrupt Enable and MRL Sensor Changed Enable bits must be set (offset 80h[5, 2]=11b)].
HP_MRLx# assertion and de-assertion at runtime is not latched until the 10-ms de-bounce ensures that
the state change is stable.
Slots with the MRL Sensor not present can use the Attention Button Pressed interrupt to generate an
event and start the Slot Power-Up sequence at runtime. (Refer to Figure 9-1.)
Figure 9-1. Slot Power-Up Timing when Power Controller Present Bit Is Set
Power valid at slot
HP_PWRENx#
Tpepv = 16 ms
HP_PWRLEDx#
HP_CLKENx#
Tpvperl = 100 ms
HP_PERSTx#
Note: HP_PWRLEDx# is not asserted if the serial EEPROM clears the Power Indicator Present bit
(offset 7Ch[4]) to 0.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
