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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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Hot Plug Support  
PLX Technology, Inc.  
9.4.1.2  
Slot Power-Up Sequencing when Power Controller Present Bit Is Set  
By default, the Power Controller Present, MRL Sensor Present, and Power Controller Control (when  
the MRL is open) bits are set to 1. When the serial EEPROM is not present, present but blank, or  
programmed with default register values, the Hot Plug Controller is initially powered up, and the  
PEX 8532 is in the following state:  
1. Hot Plug Controller is enabled for all slots.  
2. All slots are enabled to be powered up.  
3. Attention LED (HP_ATNLEDx#) and Power LED (HP_PWRLEDx#) are High on the slot chassis.  
Immediately after the PEX 8532 exits Reset (PEX_PERST# input goes high), if a downstream port’s  
MRL Sensor Present bit is set to 1 (default), the HP_MRLx# input for that slot is sampled. If the  
HP_MRLx# input is enabled and asserted (value of 0), the PEX 8532 clears the Power Controller  
Control bit to 0, to enable slot power-up. If the Power Controller Control bit is not cleared, either by  
initially enabling it (default) and asserting HP_MRLx#, or by programming both the MRL Sensor  
Present and Power Controller Control bit values to 0 in the serial EEPROM, the downstream slot is not  
powered up and remains in the disabled state, as defined in Table 9-2 and illustrated in Figure 9-3.  
If a slot’s Power Controller Present bit is set to 1, and the Power Controller Control bit is cleared to 0  
(either by initially enabling and asserting HP_MRLx# or by programming the MRL Sensor Present and  
Power Controller Control bit values to 0 in the serial EEPROM), the slot starts power-up sequencing  
with HP_PWRENx# and HP_PWRLEDx# assertion, following PEX_PERST# input de-assertion:  
If the serial EEPROM is not present, HP_PWRENx# and HP_PWRLEDx# are asserted  
approximately 6.1 ms after PEX_PERST# input is de-asserted  
If the serial EEPROM is present, HP_PWRENx# and HP_PWRLEDx# are asserted  
approximately 18.7 ms after PEX_PERST# input is de-asserted  
124  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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