February, 2007
Slot Power-Up Sequence
The power-up sequence is as follows:
1. The Hot Plug Controller drives HP_PWRLEDx# Low, to turn On the Power Indicator, and drives
HP_PWRENx# Low to turn On the external Power Controller.
2. After the programmable T
time delay following HP_PWRENx# assertion, power to the slot
pepv
is valid and the Hot Plug Controller drives HP_CLKENx# Low to turn on the Reference Clock
(PEX_REFCLKn/p) to the slot. The T time delay is specified by setting the Power
pepv
Management Hot Plug User Configuration register HPC T
Delay field (offset 1E0h[4:3])
pepv
to a non-zero value. By default, this field is cleared to 00b, indicating a 16-ms time delay from the
time HP_PWRENx# goes Low to power becoming valid at the slot.
3. After the programmable T
time delay following HP_CLKENx# assertion, the Hot Plug
pvperl
Controller de-asserts HP_PERSTx# to release slot reset. The T
time delay is specified
pvperl
in the Power Management Hot Plug User Configuration register HPC T
Delay bit
pvperl
(offset 1E0h[6]). By default, this bit is set to 1, indicating a 100-ms delay.
With this default delay, if the serial EEPROM is not present, HP_PERSTx# output is de-asserted
approximately 122 ms after PEX_PERST# input is de-asserted. However, if the serial EEPROM
is present, HP_PERSTx# output is de-asserted approximately 135 ms after PEX_PERST# input
is de-asserted.
Because the PCI Express Base r1.0a allows the host to start Configuration accesses 100 ms after the
Root Complex de-asserts its PERST# output, it is recommended that a programmed serial EEPROM
be used to clear the HPC T
Delay bit to 0, to reduce the T
time delay to 20 ms, so that
pvperl
pvperl
HP_PERSTx# is de-asserted approximately 55 ms after PEX_PERST# input is de-asserted.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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