February, 2007
Slot Power-Up Sequence
9.4.1.3
HP_PERSTx# (Reset) and HP_PWRLEDx# Output Power-Up
Sequencing when Power Controller Present Bit Is Clear
The HP_PERSTx# and HP_PWRLEDx# outputs can be used without enabling the Hot Plug Power
Controller (HP_PWRENx# and HP_CLKENx# outputs and HP_PWRFLTx# input). For example,
HP_PERSTx# can be used to reset an on-board downstream device.
If the Power Controller Present (offset 7Ch[1]) and Power Controller Control (offset 80h[10]) bits are
cleared to 0 by the serial EEPROM, HP_PERSTx# is de-asserted (High) and HP_PWRLEDx#
is asserted (Low), after the Root Complex PERST# input is de-asserted, as illustrated in Figure 9-2.
However, HP_PWRLEDx# is not asserted if the serial EEPROM also cleared the Power Indicator
Present bit (offset 7Ch[4]) to 0.
If the serial EEPROM is initially blank, causing register default values to be loaded, HP_PERSTx# is
not de-asserted and HP_PWRLEDx# is not asserted unless HP_MRLx# is Low. Therefore, if the
HP_PERSTx# and/or HP_PWRLEDx# outputs are used [and a Manually operated Retention Latch
(MRL) is not used], pull HP_MRLx# Low, to allow the outputs to toggle, regardless of whether the
serial EEPROM is blank.
HP_PERSTx# can also be toggled at runtime by toggling the Power Controller Control bit, provided
that either the Power Controller Present bit is cleared, or that HP_PERSTx# is initially de-asserted
during slot power-up sequencing, as described in Section 9.4.1.2. A value of 1 asserts HP_PERSTx#
(Low). A value of 0 de-asserts HP_PERSTx# (High).
Figure 9-2. Hot Plug Outputs when Power Controller Present and Power Controller Control Bits
Are Cleared
After Serial EEPROM Load
HP_PWRENx#
HP_PWRLEDx#
HP_CLKENx#
HP_PERSTx#
Note: HP_PWRLEDx# is not asserted if the serial EEPROM clears the Power Indicator Present bit
(offset 7Ch[4]) to 0.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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