February, 2007
Slot Power-Down Sequence
9.4.2
Slot Power-Down Sequence
Software can power-down slots by setting the Power Controller Control bit (offset 80h[10]=1). If the
MRL Sensor Present bit is set (offset 7Ch[2]=1), the Hot Plug Controller can power down the slot if the
MRL is open. Figure 9-4 illustrates the following power-down timing sequence for either event:
1. HP_PERSTx# to the port is asserted.
2. HP_CLKENx# is de-asserted to the slot 100 µs after HP_PERSTx# is asserted.
3. HP_PWRENx# is de-asserted to the slot 100 µs after HP_CLKENx# is de-asserted.
Figure 9-4. Hot Plug Automatic Power-Down Sequence
HP_PERSTx#
100 µs
HP_CLKENx#
100 µs
HP_PWRENx#
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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