February, 2007
Slot Power-Up Sequence
9.4.1.1
Configuring Hot Plug Controller Slot Power-Up Sequence Features with
Serial EEPROM
An external serial EEPROM can be used to configure the Hot Plug Controller and Hot Plug outputs.
Features can be changed by using the registers defined in Table 9-3. The Hot Plug Controller outputs
remain in the default state described in Table 9-2, before the serial EEPROM image is loaded into
the device.
After the serial EEPROM image is loaded, the Hot Plug Controller starts a power-up sequence on
each slot that has the Slot Capabilities register Power Controller Present bit set (offset 7Ch[1]=1) and
the Slot Control register Power Controller Control bit cleared (offset 80h[10]=0).
Table 9-3. Configuring Power-Up Sequence Features with Serial EEPROM
Register Bit
Hot Plug Controller and Hot Plug Output Signal Configurable Features
The Power Controller Present bit enables or disables the Hot Plug Controller on the PEX 8532
downstream ports.
If the Power Controller Present bit is cleared to 0, the Hot Plug Controller is disabled for
that slot and a power-up sequence is not executed. The slot remains in the disabled state,
as defined in Table 9-2.
If the Power Controller Present bit is enabled (set to 1), the Hot Plug Controller powers
up the slot when the MRL is closed and the Slot Control register Power Controller Control bit
is cleared (offset 80h[10]=0). Otherwise, if the MRL Sensor Present bit is disabled (cleared
to 0), the MRL’s position has no effect on powering up the slot.
Power Controller Present
(Slot Capabilities register,
offset 7Ch[1])
When enabled (set to 1), the PEX 8532 senses whether the MRL is open or closed for a slot.
If this bit is set to 1, the MRL should be Low for power-on for that slot.
If this bit is cleared to 0, the MRL position is “don’t care” for that slot.
MRL Sensor Present
(Slot Capabilities register,
offset 7Ch[2])
This field controls the delay from when HP_PWRENx# is asserted Low, to when power
is valid at a slot. (Refer to Section 9.4.1.2.) This register is Read-Only and can be set by
serial EEPROM. Values for this field are as follows:
HPC Tpepv Delay
Bits [4:3]
00b
Delay Value
16 ms (default)
32 ms
(Power Management Hot Plug
User Configuration register,
offset 1E0h[4:3])
01b
10b
64 ms
11b
128 ms
This bit controls the delay from when Power is valid at the slot to when HP_PERSTx#
is de-asserted high. (Refer to Section 9.4.1.2.) Two settings can be specified through
the serial EEPROM:
HPC Tpvperl Delay
(Power Management Hot Plug
User Configuration register,
offset 1E0h[6])
Bit 6
0
1
Delay Value
20 ms
100 ms (default)
Attention Indicator Present
When set to 1, this bit controls whether the HP_ATNLEDx# output for the slot drives out
Active-Low. Otherwise, this output is not functional on the slot.
(Slot Capabilities register,
offset 7Ch[3])
Power Indicator Present
When set to 1, this bit controls whether the HP_PWRLEDx# output for the slot drives out
Active-Low. Otherwise, this output is not functional on the slot.
(Slot Capabilities register,
offset 7Ch[4])
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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