February, 2007
Packet Arbitration
For example, programming upper = 14 and lower = 7 for VC0 posted allows each port in the station to
accumulate 14 x 8 beats = 112 beats = 112 x 20 bytes = 2,240B VC0 Posted bytes before any one port
cuts off VC0 Posted internal traffic. If there are four ports in the station, then 8,960 bytes can be stored
in the RAM without the upper limit being crossed. After a port receives more than 112 beats of VC0
posted, no further VC0 posted is forwarded from the ingress port. The egress port must drain 7 x 8 beats
before resuming VC0 posted forwarding.
The main objective is to avoid clogging the egress RAM with excessive packets of the same type that
might prevent packets of other types from making fast forward progress inside the switch. If necessary,
program the upper and lower limits.
8.3.2.5
Egress Scheduler
In each egress port, the PEX 8532 strictly follows VC and port arbitration mechanisms, as defined by
the PCI Express Base r1.0a.
Virtual Channel Arbitration
In the context of scheduling traffic in VC0 and VC1, the main goal of the egress scheduler’s
VC arbitration is to provide differentiated services between data flows within the fabric. There are three
VC arbitration choices:
• Strict priority – VC1 always prevails over VC0
• Round-Robin, or “Hardware-Fixed Arbitration” in the PCI Express Base r1.0a – Alternate
between VC0 and VC1
• Weighted Round-Robin (WRR) with 32 phases – Select VC0 or VC1, based on 32 values
programmed with the VC&T Arbitration table (refer to Table 8-3)
The strict priority selection is made by clearing the Port VC Capability 1 register Low-Priority
Extended VC Count bit to 0. The default value is strict priority, and can only be changed by serial
EEPROM initialization.
If the Low-Priority Extended VC Count bit is set to 1 (by way of serial EEPROM), then VC0 and VC1
share the low-priority pool. Within the low-priority pool, Round-Robin or Weighted Round-Robin
arbitration can be selected. The Port VC Capability 2 register VC Arbitration Capability bits
(offset 150h[1:0]) describe the two types of VC arbitration for mechanisms supported by the PEX 8532.
The Port VC Control register VC Arbitration Select bit (offset 154h[1]) defines programming.
When using Weighted Round-Robin, the 32-phase VC Arbitration Table must be programmed before
loading the table. Table entries represent one phase that is loaded by software with a low-priority VC ID
value. The VC arbiter repeatedly sequentially scans all table entries, and transmits transactions from
the VC buffer specified in the table entries. After a transaction is dispatched, the arbiter moves to the
next phase. (Refer to Table 8-3 and the VC Arbitration Table Phase n register.)
Table 8-3. Virtual Channel Arbitration Table Register Map
31 30 29 28
Phase 7
27 26 25 24
Phase 6
23 22 21 20
Phase 5
19 18 17 16
Phase 4
15 14 13 12
Phase 3
11 10 9 8
Phase 2
7 6 5 4
Phase 1
Phase 9
Phase 17
Phase 25
3 2 1 0
Phase 0
Phase 8
Phase 16
Phase 24
1B8h
1BCh
1C0h
1C4h
Phase 15
Phase 23
Phase 31
Phase 14
Phase 22
Phase 30
Phase 13
Phase 21
Phase 29
Phase 12
Phase 20
Phase 28
Phase 11
Phase 19
Phase 27
Phase 10
Phase 18
Phase 26
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
105
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