February, 2007
Packet Arbitration
8.3.2.3
PLX-Specific Relaxed Ordering
PLX Relaxed Ordering capability is supported to enhance the performance of “push-only” traffic
(Posted packets, such as Memory Writes and messages) in the PEX 8532. PLX-Specific Relaxed
Ordering mode is enabled when any bit within the PLX-Specific Relaxed Ordering Mode (Ingress)
register Enable PLX Relaxed Ordering field is set to 1:
• Port 0 or 8 – offset BFCh[7:0]
• Port 1 or 9 – offset BFCh[15:8]
• Port 2 or 10 – offset BFCh[23:16]
• Port 3 or 11 – offset BFCh[31:24]
According to PCI Ordering rules, Posted packets are not allowed to bypass previously posted packets of
the same VC&T, regardless of whether they are targeting different egress ports. In applications such as
storage area networks or IP networks, where Posted PCI Express packets are used to transmit
encapsulated data traffic through switches, unnecessary serial dependency might be created in the
Source Scheduler for those Posted packets coming from the same ingress ports, but going to different
egress ports, if strict PCI Ordering rules were followed. This can result in dramatically degraded overall
switch throughput.
The PLX-Specific Relaxed Ordering Mode (Ingress) register can be used to enable the PLX-Specific
Relaxed Ordering capability. There is an Enable bit for TCs in each ingress port. All packets are allowed
to bypass older packets from the same ingress port and TC. Packets targeting different egress ports are
free to proceed without waiting for ordering dependency to be cleared. Meanwhile, packets targeting the
same egress port are processed “in order,” because there is no performance gain.
Because the Enable bit is TC-based, taking advantage of PLX-Specific Relaxed Ordering mode requires
the PEX 8532 to be programmed with symmetric TC/VC mapping first.
Posted traffic benefits most from this mode. To take advantage of PLX-Specific Relaxed Ordering
mode, without violating other ordering rules defined by the PCI r2.3, it is suggested to restrict
outstanding traffic flow to be “Posted only” and shut down all Non-Posted packets.
There are two usage models:
• Restrict all Posted traffic requiring high-throughput in VC1 and program all TCs belonging
to VC1 to enable Relaxed Ordering.
• Software disables PLX-Specific Relaxed Ordering mode in all TCs beforehand, performing all
setups that involve Non-Posted packets, and then setting Any bit within a PLX-Specific Relaxed
Ordering Mode register Enable PLX Relaxed Ordering field (offset BFCh[31:0]) to 1 when
the system enters pure Data Transfer mode. When the Data transfer completes, disable
PLX-Specific Relaxed Ordering mode.
Note: Silicon Revisions BA/BB/BC only – A variation of this feature, Relaxed Completion Ordering,
allows only Completions to bypass Posted packets, while preserving the remainder
of PCI ordering. Refer to Section 4.3.2.2, “PEX 8532 Relaxed Completion Ordering –
Silicon Revisions BA/BB/BC Only,” for details.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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