Performance Metrics
PLX Technology, Inc.
8.3.2.4
Internal Fabric Backpressure
Internal fabric provides egress packet RAM space available status from destination stations to
source stations. The Source Scheduler never transmits a packet to overflow egress packet RAM.
Moreover, to prevent packets in a particular VC&T from occupying the majority of egress packet
RAM, and to speed up backpressure from Egress queues to Ingress queues and ultimately to external
devices in the case of congestion avoidance, VC&T-based (VC and Type – P, NP, Cpl) packet cutoff
information is passed from egress ports to each source station.
Egress queue congestion occurs when the packet arrival rate overcomes the packet dispatching rate.
There are two causes of congestion:
• Insufficient credit to transmit the packets
• Insufficient bandwidth to transmit the packets as quickly as they arrive
In either case, if the cause continues, eventually the Egress queues of the congested port fill.
The PEX 8532 utilizes a watermark mechanism to cut off additional packets from the ingress side when
the Egress queues back up. With some egress ports cut off, Ingress queues that contain packets targeting
those egress ports could then fill. A filled Ingress queue prevents additional credit to its link partner,
which causes that external device to stop transmitting packets in that VC&T.
The ITCH VC&T Threshold registers are per-VC&T-based in an egress port. All ports in a station
share the same programmed value. Each VC&T has its own upper and lower limit. If more data than the
programmed upper limit is queued, no more packets of that VC&T can be scheduled across the internal
fabric, thereby cutting off that VC&T flow. After cutting off the VC&T flow, an Egress queue eventually
drops below its lower limit, as packets are scheduled out of the egress port. This event turns on the
internal fabric VC&T-enabling flags, which allow that VC&T to resume flow. [Refer to the ITCH
VC&T Threshold_1 through ITCH VC&T Threshold_3 registers (offset C00h through C08h,
respectively) for further details.]
There are two rules used for programming the ITCH VC&T Threshold registers:
• The unit value for the upper and lower limits is equivalent to 8 beats. The maximum value
programmable in the upper limit is a function of the port width, defined in Table 8-2.
A x8 egress port can handle no more than 1,024 beats, a meaningful value for the upper and lower
limits is bounded by 1,024/8 = 128 (or 80h). In the device, the default value used by the upper and
lower limits (FFh) is larger than its maximum legal value (80h). Therefore, by default, the
backpressure mechanism is not triggered.
• The upper and lower limits must be different, with the upper number being larger than the lower
number by at least two units.
Table 8-2. VC&T Threshold Limits
Port Width
Maximum Upper Limit in Beats
x1
x2
128
256
x4
512
x8
1,024
2,048
x16
104
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
