Performance Metrics
PLX Technology, Inc.
8.3.2
Packet Arbitration
Because of CIOQ switch architecture and multiple VC support, the PEX 8532 functions with several
arbitration/scheduling points distributed in the data path from an ingress port to an egress port.
This section discusses the arbitration/scheduling/backpressure algorithm used in the Source Scheduler,
internal fabric, and egress scheduler.
8.3.2.1
Source Scheduler
Source Scheduler is essentially the VOQ scheduler depicted in Figure 8-1. The Source Scheduler
functions as follows:
• From all 32 VOQ entries (each entry represents a single packet) belonging to a single ingress port,
identifies one packet to be dispatched to the appropriate destination station, when egress RAM
space is available
• Arbitrates among multiple-ready packets from different ingress ports with a Round-Robin
mechanism
• Breaks deadlock potential by following PCI Ordering rules
Note: Packets to different egress ports are selected with oldest first criteria on a per-queue
basis. This policy offers optimum fairness and performance properties at low
complexity. Packets to different VCs are selected by allowing VC1 higher priority,
if configured as such. PCI Ordering rules are enforced.
The Source Scheduler is capable of handling variable-length packets. It can schedule one packet out
of a source station every Clock cycle, regardless of packet size.
There are two programmable fields in the Source Scheduler:
• High-Priority Virtual Channel
• PLX-Specific Relaxed Ordering
8.3.2.2
High-Priority Virtual Channel
When two VCs are enabled, packets from VC1 are scheduled with high priority by clearing the
Port VC Capability 1 register (offset 14Ch) Low-Priority Extended VC Count bit. Default setup can be
changed by serial EEPROM initialization.
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ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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