Performance Metrics
PLX Technology, Inc.
8.4.2
Single-Stream Throughput
When data flows in a single-packet stream from a fixed-ingress to fixed-egress port, its throughput can
be optimized on both the ingress and egress sides. The method for optimizing throughput on both sides
is discussed in the following sections.
8.4.2.1
Ingress Side
Accept More than One Packet in Same Symbol Time
The PEX 8532 ingress port is designed to accept incoming traffic at the fastest rate possible. For
x8 ports, the PEX 8532 allows the ending part of a TLP and beginning part of the next TLP to arrive in
the same symbol time. It also allows a partial TLP and a partial or full DLLP to simultaneously arrive.
Optimize Ingress Credit Allocation
A TLP cannot be transmitted to the switch without the switch providing sufficient ingress credits
beforehand. When a credit is advertised, it indicates a guaranteed storage available in the credit
transmitter at that time. If there is insufficient or untimely ingress credits advertised from the PEX 8532
to its link partner, the incoming TLP stream does not sustain at the highest possible rate.
Amount of Ingress Credit Required Calculation
The PEX 8532 supports up to six VC&Ts per port. The amount of ingress credits advertised in each
VC&T is expected to be sufficient to cover the round-trip delay from the time the external device
schedules a TLP for transmission in its Transaction Layer to the time the external device receives the
replenishing credit from the PEX 8532 in the same VC&T.
To enable a burst of TLPs of the same VC&T to enter the PEX 8532 without interruption, use the
following empirical equation:
Ingress_Credit_Advertised = (Round_trip_time_in_symbol times x link_width)
/ packet_size_in_bytes
Round-trip latency, which can range from 160 to 400 ns (40 to 100 symbol times), is determined by both
the PEX 8532 and external device and consists of the following:
• Latency for incoming TLP to travel the entire PEX 8532 ingress data path
• Delay from writing the first byte of the packet into ingress packet RAM until writing the last byte
of the packet into ingress packet RAM
• Latency for Source Scheduler to transmit the packet to egress packet RAM and free up the ingress
buffers for this TLP packet
• Latency for the PEX 8532’s ingress credit scheduler to generate an UpdateFC packet
• Latency for this UpdateFC DLLP to travel the PEX 8532 egress data path to SerDes
• Delay in SerDes
• Latency for this UpdateFC DLLP to travel the ingress data path of the external device
• Latency for external device to process the UpdateFC DLLP and update its Credit Limit Counter
• Latency for external device to schedule the next TLP in the same VC&T out
• Latency for the external device to move the new TLP across its egress data path to the SerDes
• Final delay in SerDes
For example, suppose a link with a 400 ns round-trip time contains eight lanes and a stream of Posted
transactions is broken into packets of 64B payload each. The amount of posted type header credit
needed to sustain a steady incoming traffic flow is approximately 100 x 8 / (16 + 64) = 10.
108
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
PLX [ PLX TECHNOLOGY ]
