February, 2007
Quality of Service (QoS) Support
8.3
Quality of Service (QoS) Support
Quality of Service (QoS) is a performance differentiation feature offered by PCI Express to manage
multiple traffic classes of different characteristics. An application assigns a Traffic Class (TC) value to
individual Transaction Layer packets, according to the QoS requested by the class to which the
transaction belongs. The static TC value tagged to each packet is dynamically mapped to a VC as it
passes through a system PCI Express-capable device. The TC value ultimately determines the relative
priority of a single packet as it traverses the PCI Express fabric, as well as the accumulated bandwidth
allocated to the packets that belong to the same class.
8.3.1
Virtual Channel (VC) Support
The PEX 8532 supports up to two Virtual Channels (VCs), VC0 and VC1. Each VC has its own buffer
resource allocation and data path. For a single port, VC configuration and property are determined by
the Virtual Channel Extended Capability Register map (offset 148h to 1C4h).
Registers described in the Virtual Channel Extended Capability Register map apply to the switch egress
and ingress ports. Registers related to packet arbitration are egress-specific, whereas registers defining
TC/VC mapping and Low-Priority VC Count are applicable to both egress and ingress ports. [Refer to
Table 11-10, “PEX 8532 Virtual Channel Extended Capability Register Map (All Ports),” for further
Virtual Channel mapping information.]
Virtual Channel and traffic labeling allow independent physical resources to handle differentiated
traffic. The VC0 Resource Control and VC1 Resource Control registers (offsets 15Ch and 168h,
respectively) contain bits that control TC/VC mapping.
Across various ports, the PEX 8532 supports both symmetric and asymmetric TC/VC mapping. In the
latter approach, the TC/VC mapping is port-independent and configured with different values per port.
The PEX 8532 default configuration sets all TC[7:0] to VC0, as provided in the TC/VC0 Map bits.
For applications requiring two VCs, TC[7:1] can be mapped to VC1 by removing them from the TC/
VC0 Map bits and adding them to the TC/VC1 Map bits.
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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