February, 2007
Theoretical Upper Limit
8.4.1.3
Transaction Layer Overhead
All PCI Express payloads are encapsulated in a TLP. A TLP contains a header portion that provides the
PEX 8532 with routing information for the packet. The header can be 12 or 16 bytes.
According to the PCI Express Base r1.0a, Maximum Payload Size (MPS) can range from 128 to
4,096 bytes. The PEX 8532 supports MPS of up to 256 bytes.
The Device Control register Maximum Payload Size field (offset 70h[7:5]) default MPS is 128 bytes.
Software can change the default value; however, the entire system must have a consistent MPS.
In general, longer payloads are more efficient, but require more on-chip resources to buffer, and can
cause much worse hot spot congestion in bursty traffic flows.
A TLP can also incur additional overhead when end-to-end data integrity is essential. In such cases,
a 4-byte ECRC is added as another type of overhead to the end of the packet.
Note: Refer to the Device Control register Maximum Payload Size field (offset 70h[7:5])
for MPS limitations.
8.4.1.4
PCI Express Efficiency Upper Bound Summary
Table 8-4 summarizes PCI Express inherent efficiency for 0B, 4B, 8B, 40B, 128B, 256B, and 4,096B
payload sizes on various negotiated link widths. The 4,096B table row is provided for reference only, as
the PEX 8532 supports MPS of up to 256 bytes.
The table columns provide three types of variations:
• Comparing to raw SerDes bandwidth of 2.5 Gbps versus 2.0 Gbps after 8b/10b decoding.
• 0ꢀ additional DLLP generation versus 100ꢀ DLLP generation, assuming traffic is equal in both
directions. 0ꢀ DLLP assumes that DLLP traffic is not injected into the TLP stream, such as a
uni-directional traffic stream. 100ꢀ DLLP assumes that for every TLP transmitted, an additional
ACK DLLP and UpdateFC DLLP are generated in the reverse direction for a bi-directional fully
loaded traffic stream.
• Non-payload TLP overhead of 12B versus 20B (16B header + ECRC).
In summary, the larger the payload, the more efficient the PCI Express communication. For 256-byte
Maximum Payload Size supported by the PEX 8532, the limit efficiency compared to the raw 2.5-Gbps
bandwidth is between 68 to 73.92ꢀ.
Note: Not all factors are reflected in this table. SKIP Ordered-Set drops another 0.3%.
Any credit shortage or transient congestion can significantly drop.
Table 8-4. Throughput Theoretical Upper Limit
2.5 Gbps Raw Bandwidth
Bytes of
2.0 Gbps Raw Bandwidth after 8b/10b Decoding
0% DLLP 100% DLLP
0% DLLP
100% DLLP
Payload
12B
20B+
0.00ꢀ
12B
20B+
0.00ꢀ
12B
20B+
0.00ꢀ
12B
20B+ ECRC
0.00ꢀ
0
4
0.00ꢀ
13.28ꢀ
22.80ꢀ
53.12ꢀ
68.96ꢀ
73.92ꢀ
79.36ꢀ
0.00ꢀ
8.00ꢀ
0.00ꢀ
16.60ꢀ
28.50ꢀ
66.40ꢀ
86.20ꢀ
92.40ꢀ
99.20ꢀ
0.00ꢀ
10.00ꢀ
18.10ꢀ
52.50ꢀ
77.80ꢀ
87.40ꢀ
98.80ꢀ
10.00ꢀ
17.68ꢀ
46.88ꢀ
65.44ꢀ
71.84ꢀ
79.20ꢀ
6.64ꢀ
12.50ꢀ
22.10ꢀ
58.60ꢀ
81.80ꢀ
89.80ꢀ
99.00ꢀ
8.30ꢀ
8
14.48ꢀ
42.00ꢀ
62.24ꢀ
69.92ꢀ
79.04ꢀ
12.24ꢀ
38.00ꢀ
59.36ꢀ
68.00ꢀ
78.88ꢀ
15.30ꢀ
47.50ꢀ
74.20ꢀ
85.00ꢀ
98.60ꢀ
40
128
256
4,096
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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