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PEX8532-BB25BI 参数 Datasheet PDF下载

PEX8532-BB25BI图片预览
型号: PEX8532-BB25BI
PDF下载: 下载PDF文件 查看货源
内容描述: [PCI Bus Controller, CMOS, PBGA680, 35 X 35 MM, 2.23 MM HEIGHT, 1 MM PITCH, BGA-680]
分类和应用: 时钟数据传输PC外围集成电路
文件页数/大小: 512 页 / 4374 K
品牌: PLX [ PLX TECHNOLOGY ]
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Performance Metrics  
PLX Technology, Inc.  
8.2.3  
RAM and Queue Size  
Table 8-1 defines the RAM and Queue Size built into the PEX 8532. The smallest unit of ingress and  
egress packet RAM is defined as a beat, which can store 20 bytes of data. In the PEX 8532, the smallest  
packet (12B header) takes 1 beat to store in a packet RAM, and the largest packet (16B header + 256B  
payload + 4B digest = 276B) takes 14 beats to store in packet RAM.  
In Table 8-1, the number 32 under the cell Ingress VOQ Entries, Per Port indicates the maximum  
number of VOQ entries allocated to each ingress port. Each VOQ entry holds one Transaction Layer  
packet. For ingress ports, the incoming packet can travel to two destination stations, with each station  
containing up to four egress ports. Also, for egress ports, up to two VCs are supported, with each VC  
potentially having three different packet types – Posted, Non-Posted, and Completion (P, NP, and Cpl,  
respectively).  
Each port on the egress side can contain up to six queues, to hold packets from two supported VCs and  
three supported packet types. A queue that stores packets of a unique VC and a unique type is referred to  
as a VC&T queue. Again, some queues can be completely empty and some queues can contain more  
than one packet. The maximum number of packets held by a single egress port is limited by the number  
of egress packet RAM beats allocated to that port.  
It can be calculated from Table 8-1 that the total packet RAM size for the PEX 8532 is 136,960 bytes.  
Assume the maximum Transaction Layer Packet (TLP) size is 276B with a Maximum Payload Size  
(MPS) of 256B. Theoretically, the PEX 8532 can store up to 496 MPS packets.  
Table 8-1. PEX 8532 Data Structure Size  
Data Structure Name  
Ingress Packet Name  
Ingress VOQ Entries  
Per Port  
Programmable  
32  
Per Station  
Overall  
55,040 bytes  
256  
1,376 beats or  
27,520 bytes  
128  
1,024 beats or  
20,480 bytes for  
1 to 2 ports;  
2,048 beats or  
40,960 bytes  
Egress Packet RAM  
81,920 bytes  
48  
512 beats or 10,240 bytes  
for 3 to 4 ports  
Egress VC&T Queues  
6
24  
100  
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book  
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6  
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