February, 2007
Port-to-Station Aggregation
8.2.2
Port-to-Station Aggregation
As previously stated, a single PEX 8532 PCI Express station is aggregated from multiple ports,
provided that the combined port width is less than or equal to 16 lanes. Figure 8-1 redraws the
PEX 8532 Transaction Layer architecture, by explicitly dividing a PCI Express station into individual
ingress and egress parts.
In a PCI Express source station, the write port to the ingress packet RAM is shared by up to four ingress
ports in a Time Domain Multiplex (TDM) manner. The wider the port, the more TDM slots are assigned
to that port. Within VOQs of a single source station, if multiple packets from different ingress ports are
available to be dispatched to the same destination, a Round-Robin arbiter controls which ingress port to
select next.
Moving to the internal fabric, the Read ports to ingress packet RAM and Write ports to egress packet
RAM are controlled by the PLX implementation of the CIOQ scheduling algorithm, where a unit in
scheduling is a station, rather than a port.
In a PCI Express destination station, the Read port to the egress packet RAM is shared by up to four
egress ports in a TDM manner as well. Furthermore, there are four independent egress schedulers.
Egress schedulers follow Virtual Channel arbitration, as required by the PCI Express Base r1.0a.
Figure 8-1. PEX 8532 Queuing Data Structures
Station 0
Source Station 0
1,376 x 20B =
Destination Station 0
Internal Fabric
2,048 x 20B =
40,960B
Egress Packet
RAM
27,520B
Ingress Packet
RAM
P0 Ingress
P0 Egress
P1 Ingress
P2 Ingress
P1 Egress
P2 Egress
Egress
Scheduler
32- entry P0 VOQ Ctl
32-entry P1 VOQ Ctl
32-entry P2 VOQ Ctl
32-entry P3 VOQ Ctl
P0 VC link list
P1 VC link list
P2 VC link list
P3 VC link list
Egress
Scheduler
P3 Ingress
Egress
Scheduler
P3 Egress
Egress
Scheduler
Destination Station 1
Source Station 1
2,048 x 20B =
40,960B
Egress Packet
RAM
1,376 x 20B =
27,520B
Ingress Packet
RAM
P8 Ingress
P8 Egress
P9 Ingress
P9 Egress
Egress
Scheduler
Support
P8 VC link list
P9 VC link list
P10 VC link list
P11 VC link list
32-entry P8 VOQ Ctl
32-entry P9 VOQ Ctl
32-entry P10 VOQ Ctl
32-entry P11 VOQ Ctl
P10 Ingress
P10 Egress
Egress
Scheduler
P11 Ingress
Egress
Scheduler
P11 Egress
Egress
Scheduler
Station 1
ExpressLane PEX 8532AA/BA/BB/BC 8-Port/32-Lane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.6
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