Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.16.5
AUDIO CONFIGURATION
The configuration parameters are selected using two configuration registers, ACON1 and ACON2.
The ACON1 register is locally buffered. The download from the shadow register into the working register is performed
when a DMA protection address is reached or immediately when both interfaces are not active (switched off, initial state).
Table 103 Audio Configuration Register 1 (ACON1)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
F4
AUDIO_MODE [2:0]
MAXLEVEL [6:0]
31 to 29
28 to 22
RW defines interface activation and combination
RW defines the maximum allowed absolute value for the most
significant byte of an audio sample
A1_SWAP
A2_SWAP
21
20
RW defines if input (captured) data is stuffed in little-endian or
big-endian format for A1 (4 byte swap if set)
RW defines if input (captured) data is stuffed in little-endian or
big-endian format for A2 (4 byte swap if set)
WS0_CTRL [1:0]
WS0_SYNC [1:0]
WS1_CTRL [1:0]
WS1_SYNC [1:0]
WS2_CTRL [1:0]
WS2_SYNC [1:0]
WS3_CTRL [1:0]
WS3_SYNC [1:0]
WS4_CTRL [1:0]
WS4_SYNC [1:0]
19 and 18
17 and 16
15 and 14
13 and 12
11 and 10
9 and 8
RW function control for WS0 line
RW pulse position and width control for WS0 line
RW function control for WS1 line
RW pulse position and width control for WS1 line
RW function control for WS2 line
RW pulse position and width control for WS2 line
RW function control for WS3 line
7 and 6
5 and 4
RW pulse position and width control for WS3 line
RW function control for WS4 line
3 and 2
1 and 0
RW pulse position and width control for WS4 line
Table 104 Audio Configuration Register 2 (ACON2)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
F8
A1_CLKSRC [4:0]
A2_CLKSRC [4:0]
INVERT_BCLK1
INVERT_BCLK2
BCLK1_OEN
31 to 27
26 to 22
21
RW defines the bit clock source for A1
RW defines the bit clock source for A2
RW input or output BCLK1 with inverted polarity
RW input or output BCLK2 with inverted polarity
RW output enable BCLK1 (active LOW)
RW output enable BCLK2 (active LOW)
20
19
BCLK2_OEN
18
1998 Apr 09
118
NXP [ NXP ]
