Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Each interface, A1 and A2, uses its own Time Slot List (TSL) when working independently of each other. The shaded
areas are valid for combined processing of TSL1 and TSL2 only. In these modes, TSL1 or TSL2 are used interleaved or
concatenated, to achieve one single TSL with up to 32 records. Both parts of the list control both interface circuits in
parallel. All four DMA channels are available. The TSLs are write only.
Table 101 Time slot list structure
RECORD
TSL1
TSL2
STRUCTURE
16 DWORDS (OFFSET: 180 TO 1BCH)
16 DWORDS (OFFSET: 1C0 TO 1FCH)
BIT#
NAME
WS0
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
WS1
WS2
WS3
WS4
reserved
DIS_A1 [1]
DIS_A1 [0]
SDW_A1
SIB_A1
SF_A1
LF_A1
BSEL_A1 [2]
BSEL_A1 [1]
BSEL_A1 [0]
DOD_A1 [1]
DOD_A1 [0]
LOW_A1
reserved
DIS_A2 [1]
DIS_A2 [0]
SDW_A2
SIB_A2
8
SF_A2
7
LF_A2
6
BSEL_A2 [2]
BSEL_A2 [1]
BSEL_A2 [0]
DOD_A2 [1]
DOD_A2 [0]
LOW_A2
EOS
5
4
3
2
1
0
1998 Apr 09
116
NXP [ NXP ]
