Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.10 SUBADDRESS 09H
Table 36 Luminance control SA 09, D7 to D0
FUNCTION
APER/BPSS BIT
LOGIC LEVEL
DATA BIT
Aperture factor (APER); see Figs 12 to 17
Aperture factor = 0
APER1
APER0
APER1
APER0
APER1
APER0
APER1
APER0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
Aperture factor = 0.25
Aperture factor = 0.5
Aperture factor = 1.0
Update time interval for analog AGC value (UPTCV)
Horizontal update (once per line)
UPTCV
UPTCV
0
1
D2
D2
Vertical update (once per field)
Vertical blanking luminance bypass (VBLB)
Active luminance processing
VBLB
VBLB
0
1
D3
D3
Chrominance trap and peaking stage are disabled
during VBI lines determined by VREF = 0; see Table 45
Aperture band-pass (centre frequency) (BPSS)
Centre frequency = 4.1 MHz
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
BPSS1
BPSS0
0
0
0
1
1
0
1
1
D5
D4
D5
D4
D5
D4
D5
D4
Centre frequency = 3.8 MHz; note 1
Centre frequency = 2.6 MHz; note 1
Centre frequency = 2.9 MHz; note 1
Prefilter active (PREF); see Figs 12 to 17
Bypassed
Active
PREF
PREF
0
1
D6
D6
Chrominance trap bypass (BYPS)
Chrominance trap active; default for CVBS mode
Chrominance trap bypassed; default for S-video mode
BYPS
BYPS
0
1
D7
D7
Note
1. Not to be used with bypassed chrominance trap.
1999 Jul 01
57
NXP [ NXP ]
