Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.9 SUBADDRESS 08H
Table 35 Sync control SA 08, D7 to D5, D3 to D0
FUNCTION
CONTROL BIT
LOGIC LEVEL
DATA BIT
Vertical noise reduction (VNOI)
Normal mode (recommended setting)
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
VNOI1
VNOI0
0
0
0
1
1
0
1
1
D1
D0
D1
D0
D1
D0
D1
D0
Fast mode [applicable for stable sources only;
automatic field detection (AUFD) must be disabled]
Free running mode
Vertical noise reduction bypassed
Horizontal PLL (HPLL)
PLL closed
HPLL
HPLL
0
1
D2
D2
PLL open; horizontal frequency fixed
Horizontal time constant selection (HTC1 and HTC0)
TV mode (recommended for poor quality TV signals
only; do not use for new applications)
HTC1 and HTC0
HTC1 and HTC0
00
01
D4 and D3
D4 and D3
VTR mode (recommended if a deflection control circuit
is directly connected to SAA7113H)
Reserved
HTC1 and HTC0
HTC1 and HTC0
10
11
D4 and D3
D4 and D3
Fast locking mode (recommended setting)
Forced ODD/EVEN toggle FOET
ODD/EVEN signal toggles only with interlaced source
FOET
FOET
0
1
D5
D5
ODD/EVEN signal toggles fieldwise even if source is
non-interlaced
Field selection (FSEL)
50 Hz, 625 lines
60 Hz, 525 lines
FSEL
FSEL
0
1
D6
D6
Automatic field detection (AUFD)
Field state directly controlled via FSEL
Automatic field detection
AUFD
AUFD
0
1
D7
D7
1999 Jul 01
56
NXP [ NXP ]
