Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
handbook, halfpage
handbook, halfpage
AD2
AD1
AD2
AI22
AI21
CHROMA
AI22
CHROMA
AI21
LUMA
AI12
AI11
LUMA
AI12
AD1
AI11
MHB342
MHB341
Fig.35 Mode 0; CVBS (automatic gain).
Fig.36 Mode 1; CVBS (automatic gain).
handbook, halfpage
handbook, halfpage
AD2
AD1
AD2
AD1
AI22
AI21
AI22
AI21
CHROMA
CHROMA
LUMA
LUMA
AI12
AI11
AI12
AI11
MHB343
MHB344
Fig.37 Mode 2; CVBS (automatic gain).
Fig.38 Mode 3; CVBS (automatic gain).
handbook, halfpage
handbook, halfpage
AD2
AD1
AD2
AD1
AI22
AI21
CHROMA
AI22
AI21
CHROMA
LUMA
AI12
AI11
LUMA
AI12
AI11
MHB346
MHB345
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1
(full luminance bandwidth).
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1
(full luminance bandwidth).
Fig.39 Mode 6; Y + C (gain channel 2 adjusted via
GAI2).
Fig.40 Mode 7; Y + C (gain channel 2 adjusted via
GAI2).
handbook, halfpage
AD2
handbook, halfpage
AD2
AI22
AI21
CHROMA
AI22
AI21
CHROMA
LUMA
AI12
AI11
LUMA
AI12
AI11
AD1
AD1
MHB348
MHB347
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1
(full luminance bandwidth).
I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1
(full luminance bandwidth).
Fig.41 Mode 8; Y + C (gain channel 2 adapted to Y
gain).
Fig.42 Mode 9; Y + C (gain channel 2 adapted to Y
gain).
1999 Jul 01
53
NXP [ NXP ]
