Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.4 SUBADDRESS 03H
Table 30 Analog control 2 (AICO2) SA 03
FUNCTION
LOGIC LEVEL
DATA BIT
Static gain control channel 1 (GAI18) (see SA 04)
Sign bit of gain control
see Table 31
see Table 32
D0
D1
Static gain control channel 2 (GAI28) (see SA 05)
Sign bit of gain control
Gain control fix (GAFIX)
Automatic gain controlled by MODE3 to MODE0
Gain is user programmable via GAI1 + GAI2
0
1
D2
D2
Automatic gain control integration (HOLDG)
AGC active
0
1
D3
D3
AGC integration hold (freeze)
White peak off (WPOFF)
White peak control active
White peak off
0
1
D4
D4
AGC hold during vertical blanking period (VBSL)
Short vertical blanking (AGC disabled during equalization and serration
pulses)
0
1
D5
D5
Long vertical blanking (AGC disabled from start of pre-equalization pulses
until start of active video (line 22 for 60 Hz, line 24 for 50 Hz)
HL not reference select (HLNRS)
Normal clamping if decoder is in unlocked state
Reference select if decoder is in unlocked state
0
1
D6
D6
15.2.5 SUBADDRESS 04H
Table 31 Gain control analog (AICO3); static gain control channel 1 GAI1 SA 04, D7 to D0
SIGN
BIT
CONTROL BITS D7 TO D0
DECIMAL
VALUE
GAIN
(dB)
GAI18
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
0...
≈−3
≈0
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
...117...
...511
≈6
1999 Jul 01
54
NXP [ NXP ]
