Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
Table 45 VREF pulse position and length VRLN SA 10 (D3)
VREF AT 60 Hz 525 LINES
VRLN
VREF AT 50 Hz 625 LINES
0
1
0
1
Length
240
242
286
288
Line number
Field 1(1)
Field 2(1)
first
last
258 (261)
first
last
259 (262)
first
24
last
309
622
first
23
last
310
623
19 (22)
18 (21)
282 (285) 521 (524) 281 (284) 522 (525)
337
336
Note
1. The numbers given in parenthesis refer to ITU line counting.
Table 46 Fine position of HS HDEL0 and HDEL1 SA 10 (D5 and D4)
CONTROL BITS D5 AND D4
FINE POSITION OF HS (STEPS IN 2/LLC)
HDEL1
HDEL0
0
1
2
3
0
0
1
1
0
1
0
1
Table 47 Output format selection OFTS0 and OFTS1 SA 10 (D7 and D6); see Tables 6 and 7
CONTROL BITS D7 AND D6
V-FLAG GENERATION IN
SAV/EAV-CODES
OFTS1
OFTS0
Standard ITU 656-format
0
0
1
1
0
1
0
1
V-flag in SAV/EAV is generated by VREF
V-flag in SAV/EAV is generated by data-type
Reserved
1999 Jul 01
61
NXP [ NXP ]
