Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
FUNCTION
50 Hz
CHBW/CSTD
BIT
LOGIC
LEVEL
DATA BIT
60 Hz
Clear DTO (CDTO)
Disabled
CDTO
CDTO
0
1
D7
D7
Every time CDTO is set, the internal subcarrier DTO phase is reset to
0° and the RTCO output generates a logic 0 at time slot 68 (see
external document “RTC Functional Description”, available on
request). So an identical subcarrier phase can be generated by an
external device (e.g. an encoder).
15.2.16 SUBADDRESS 0FH
Table 42 Chrominance gain control SA 0F (D6 to D0)
CONTROL BITS D6 TO D0
CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0
CHROMINANCE GAIN VALUE
(IF ACGC IS SET TO LOGIC 1)
Minimum gain (0.5)
Nominal gain (1.125)
Maximum gain (7.5)
0
0
1
0
1
1
0
0
1
0
0
1
0
1
1
0
0
1
0
0
1
Table 43 Chrominance gain control SA 0F (D7)
AUTOMATIC CHROMINANCE GAIN CONTROL ACGC
D7
ACGC
On
0
1
Programmable gain via CGAIN6 to CGAIN0
15.2.17 SUBADDRESS 10H
Table 44 Format/delay control SA 10 (D2 to D0)
CONTROL BITS D2 TO D0
YDEL1
LUMINANCE DELAY
COMPENSATION (STEPS IN 2/LLC)
YDEL2
YDEL0
−4...
...0...
...3
1
0
0
0
0
1
0
0
1
1999 Jul 01
60
NXP [ NXP ]
