Philips Semiconductors
Product specification
9-bit video input processor
SAA7113H
15.2.6 SUBADDRESS 05H
Table 32 Gain control analog (AICO4); static gain control channel 2 GAI2 SA 05, D7 to D0
SIGN BIT
(SA 03, D1)
CONTROL BITS D7 TO D0
DECIMAL
VALUE
GAIN
(dB)
GAI28
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
0...
≈−3
≈0
0
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
...117...
...511
≈6
15.2.7 SUBADDRESS 06H
Table 33 Horizontal sync begin SA 06, D7 to D0
CONTROL BITS D7 TO D0
HSB5 HSB4 HSB3
DELAY TIME
(STEP SIZE = 8/LLC)
HSB7
HSB6
HSB2
HSB1
HSB0
−128...−109 (50 Hz)
−128...−108 (60 Hz)
−108 (50 Hz)...
forbidden (outside available central counter range)
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
−107 (60 Hz)...
...108 (50 Hz)
...107 (60 Hz)
109...127 (50 Hz)
108...127 (60 Hz)
forbidden (outside available central counter range)
Recommended value
for raw data type;
see Fig.24
1
1
1
0
1
0
0
1
15.2.8 SUBADDRESS 07H
Table 34 Horizontal sync stop SA 07, D7 to D0
CONTROL BITS D7 TO D0
HSS5 HSS4 HSS3
DELAY TIME
(STEP SIZE = 8/LLC)
HSS7
HSS6
HSS2
HSS1
HSS0
−128...−109 (50 Hz)
−128...−108 (60 Hz)
−108 (50 Hz)...
forbidden (outside available central counter range)
1
1
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
−107 (60 Hz)...
...108 (50 Hz)
...107 (60 Hz)
109...127 (50 Hz)
108...127 (60 Hz)
forbidden (outside available central counter range)
Recommended value
for raw data type;
see Fig.24
0
0
0
0
1
1
0
1
1999 Jul 01
55
NXP [ NXP ]
